The present invention relates generally to charge pump circuits and more particularly pertains to variable charge pump circuits adapted for providing any of several target output voltage levels.
Many types of memory devices require high voltages for reading, programming and erasing instructions. This is true for memory with page, bulk, and sector erases.
The most common approach to generate high internal voltages is to use charge pump circuits to boost a voltage supplied to the memory circuit. A charge pump circuit uses an array of capacitors to increase the supply voltage. A low power source is coupled to a charge pump circuit to generate necessary high voltages for erasing, reading and programming operations in a memory.
FIG. 1 shows a schematic diagram of a typical two-stage charge pump circuit 100 that generates a boosted output voltage Vpump with a magnitude that is greater than the magnitude of a supply voltage Vcc supplied by a source 102, such as from an external pin of the memory chip. The voltage source 102 is coupled to a first diode-connected NMOS transistor 104. The source of this first NMOS transistor 104 is coupled to a capacitor 106 and to a second diode-connected NMOS transistor 110. The source of the second NMOS transistor 110 is coupled to a second capacitor 108 and to a third NMOS transistor 112. The third transistor 112 has its gate connected to its drain and its source connected to the output voltage Vpump. The other terminals 114 and 118 of the capacitors 106 and 108 receive respective clock signals CK and CKN of opposite phase. The internal high voltages are obtained by boosting the series of capacitances 106, 108 with the internal supply voltage Vcc. The capacitors 106 and 108 store and transfer charge at the rate of the clocks. Node A is the junction between the capacitor 106 and the source of the diode-connected NMOS transistor 110. Node B is the junction between the capacitor 108 and the diode-connected NMOS transistor 112. The voltage at node A equals the sum of the voltages of the capacitor 106 and Vcc. The voltage at node B equals the voltage of the capacitor 108. The output voltage (Vpump) is the sum of the voltages at nodes A and B. Depending on the efficiency of the charge pump circuit 100, the pump output voltage (Vpump) is the amount of voltage that the transistor 112 delivers to the output terminal. A first regulator may be provided with feedback from the pump output voltage to rapidly turn the charge pump on and off in order to minimize ripples in the pump output voltage.
In a two-stage charge pump circuit like that shown in FIG. 1, the pump output voltage Vpump can be less than the maximum voltage that the charge pump circuit 100 can possibly deliver. For example, the charge pump may be called upon to supply any of several different output voltages (Vpump), only one of which is near the maximum. More generally, for n-stage pump circuit the maximum pump output (Vout,max) equals to (n+1)* Vcc. The current that the charge pump is able to furnish is Iout=f(Vddxc2x7NPxc2x7CP/NSxc2x7TCK), when NP is the number of parallel stages, NS is the number of series stages, CP is the capacitance value and TCK is the charge pump clock period. The clock signals CK and CKN define the charge transfer rate from the internal power supply 114. Equivalently, the faster the clock rate, the faster the pump voltage reaches the target voltage.
Usually, a charge pump output (Vpump) that is significantly less than the maximum output (Vmax) experiences a ripple voltage signal caused by the sharing of charge between the capacitance of the pump circuit and that of the load circuit. The frequency of the ripple voltage coincides with the charge and discharge cycles of the clock. The output voltage rises above (overshoots) the target voltage during a charge cycle, and then drops again as a function of the RC discharge of the load and the load capacitance CL. The level of voltage overshoots is proportional to the difference between the maximum pump output voltage, Vmax and the pump output (Vpump). In another word, the voltage overshoot is proportional to the excess charge being dumped into the load capacitance.
This ripple phenomenon is very critical when a charge pump circuit 100 has to provide any of several different regulated Vout values. When a single charge pump circuit 100 has to furnish more than one Vpump value ranging from a very low to a very high value. In this case, the pump boost capacitor has to be larger in order to guarantee that the charge pump circuit 100 is able to furnish sufficient current at the highest voltage, but is over efficient at furnishing current at very low Vpump values, generating in this last case very high ripple. Because the overshoot is due to pure charge sharing between internal pump capacitance and external load, the lower the regulated pump output, the higher the charge sharing and the higher the voltage overshoot.
Referring to FIGS. 2A, 2B and 2C, the graphs of three different pump voltage outputs, VA, VB (=2.VA), and VC (=4.VA), from the same charge pump circuit plotted against time show that Vpump and Iout are strictly depending on target pump value and charge pump behavior. When charge pump specification such as Vmax and loadmax are known, the dimension of the pump can be defined in order to achieve the best efficient pump. The dimension of the pump 100 is identified with minimum consumption, area, and the number of stages. FIG. 2A shows the lowest pump output voltage VA with the highest overshoot problem because the charge pump circuit is over efficient for the given load capacitance. FIG. 2B shows a lower overshoot problem for the higher pump voltage VB because the load is better matched to the pump circuit 100. FIG. 2C shows almost no overshoot problem for the highest pump voltage VC near Vmax, which is the best load match for this charge pump circuit.
In one attempt to solve the overshoot problem in charge pumps, the U.S. Pat. No. 6,370,046 entitled xe2x80x9cUltra-Capacitor Based Dynamically Regulated Charge Pump Power Converterxe2x80x9d by Nebrigic et al. (the ""046 patent), uses a power converter to provide electrical power by dynamically controlling a switch matrix of the charge pump that includes a flying ultra capacitor. The ""046 dynamically provides the power upon demand by sensing the output voltage and changing the operating frequency of the charge pump in response. In particular, the dynamic controller operates a capacitive power output stage to pump charge at a rate to maintain an output voltage Vout across a load capacitor. The dynamic controller discharges a fly capacitor into the load capacitor when the output voltage drops below a reference voltage. The closed loop dynamic control allows for maintaining a desired output voltage by charging and discharging the flying ultra capacitor. The ""046 patent also discloses a two state controller that switches a flying ultra capacitor at a slow rate to produce increased output power. The two states controller maintains a predetermined voltage ripple across the flying ultra capacitor to attain efficient charge transfer to the output capacitor.
An object of the invention is to provide a charge pump circuit with a minimum-ripple pump output voltage and at the same time maintain the basic structure of charge pump and of regulator.
The object is met by a charge pump circuit with variable load. The charge pump circuit comprises one or more stages operable to receive a supply voltage and generate one or more pump voltages. A plurality of loads are connectable to the charge pump output, each load associated with a specific target pump voltage. A load selector means couples a selected load to the output according to the target pump voltage.
In conclusion, a new approach to select dynamically the best load for a pump as a function of the target output voltage.
In another embodiment, a regulator may be provided to monitor the output for unacceptable levels of overshoot and attach an additional load in the event such unacceptable overshoot is detected.